The Sam's Zilog Z80B clock speed is always 6MHz, but RAM delays mean it can’t use all the cycles it gets.
- Instructions running in external RAM always run at full CPU speed.
- Instructions in internal RAM get roughly the full number of cycles, but all instruction lengths are rounded up to boundaries of 4 t-states (because this is the next time at which RAM is available for fetching the next instruction). Typical code will go about 10%-20% more slowly for this reason.
- With the screen on in modes 2,3 or 4, you lose about 20% of available memory cycles
- With the screen on in modes 1 you lose about 35 % of available memory cycles
Some instructions which don’t use memory cycles are not affected by some of these conditions, so they can appear to go faster than would otherwise be expected. The full detail is rather complicated and was the subject of a very good article in Based On An Idea...
The Z80B's in most SAM's are a Goldstar Z8400BPS.
From Dave Park
I remember Alan Miles and Bruce Gordon having a discussion about exactly this. Arnie Gardner, Tony Ianiri and I were present.
They wanted to start using one of the better CPUs available at the time. They were looking at a Hitachi chip, and the Z180, which was very similar to the Hitachi chip but quite a bit more expensive. Both had an MMU and could address 1MB. They knew they needed to decide the target CPU *first* before designing the ASIC.
Given their limited budget and difficulty getting samples from Zilog (I remember Hitachi day because Bruce was bouncing around the place like a little kid) they decided to go with a 6 or 8 MHz plain Z80 and use the ASIC to displace everything else they could except RAM.
They were *this* close to using the Hitachi (looks it up) HD64180. It was too new and premium priced at the time.